Resume for Sriram Subramanian


§ (425) 463 8386 § § § LinkedIn: SriramHere


To seek a challenging full time opportunity as a Senior Software Design Engineer in Test



·         Strong Software Design/ Coding/ Testing skills

·         Well-versed with Microsoft’s Standard Test and Development Processes

·         Experience shipping products across multiple versions

·         Team player with a Can-Do Attitude, Good Interpersonal, Mentoring and Leadership skills



·         Project Management

·         Passion for Quality

·         Test Specification Development

·         Software Design and Implementation

·         End To End Testing/ Scenario Testing

·         Black Box and White Box Testing




C/ C++, C#, Perl/ PowerShell/ JavaScript, SQL


Virtualization, Cloud Computing, Social Computing, Distributed Computing


Agile Programming, Test Driven Development (TDD), Threat Modeling


Visual Studio Team System 2010, Windows Test Technology(WTT), XPerf, PerfTrack, Visio


Windows Server/ Windows 7/ Linux, Hyper-V, SQL Server, Silverlight


Microsoft Corporation – Redmond, WA

Jan 2006 to Present

Software Design Engineer in Test

ü  Owned End to End Performance Testing for Next Generation Windows Test Technology framework

o    Identified performance bottlenecks at component level (Resource Allocation & Submission Mgr)

o    Implemented performance tracking and reporting mechanism on a build-by-build basis


o    Over 40% improvements in End to End performance of the Enterprise Build Verification Test (EBVT) system.

o    Saving of more than 4 hours on daily EBVT runs for various Windows Code Branches

ü  End to End Test Ownership for Microsoft Hyper-V Server 2008 R2 (aka Boot From Flash SKU)

o    Led test efforts for the SKU throughout the Windows 7 product milestone from Planning to Release

o    Owned End to End testing including Functional, Performance and Scalability Testing

o    Co-Authored Boot from Flash Setup Documentation for the hardware manufacturers

o    Contributed to key Design decisions including to have Paging Enabled by default


o    Competitive product forced to be offered for free, resulting in Strategic Win for Microsoft

ü  Led collecting Code Coverage metric for Hyper-V role on Windows Server 2008.

o    Fixed instrumentation issues on Hyper-V binaries, Coordinated coverage Test Passes and Reported first official Code Coverage metric on Hyper-V binaries

o    Educated feature test owners to increase test coverage based on Code Coverage Analysis


o    Hyper-V ready for Sign-off for RTM on Code Coverage Shipping Quality Gate

o    Increased test coverage on Hyper-V features in Windows Server 2008 R2

ü  Test ownership for various Hyper-V and Visual C++ Compiler Features

o    Designed and implemented high quality test plan and automation for Hyper-V Meta-Operations including VHD Merging, Compaction and Expansion

o    Designed and implemented high quality test plan and automation for Visual C++ Optimizations and features including Stack-Packing, X64 Intrinsics, Errors and Warnings


o    Provided more than 90% Block Coverage on individual features

o    Reduced more than 80% of manual testing efforts, resulting in shorter feature test pass time of less than 4 hours from 2 days

ü  Designed and Implemented an Extensible Framework for Fuzzing Device Driver IOCTLs


o    Decreased the entry bar for Device Driver Fuzz testing for Hyper-V Virtual Devices

o    Enabled adding Fuzzing for new Device Drivers with considerably less time and effort (over 40% reduction in code)

archpro design automation (now Synopsis) – bangalore

May 2005 to Dec 2005

Sr. Software Engineer

ü  Query Mechanism for Multi-Voltage Design Constructs

o    Designed and Implemented a mechanism to query and report Multi-Voltage Design Constructs

o    Implemented a simple Query Language to facilitate such a query mechanism


o    Enabled shipping industry’s first Multi-Voltage Design Verification solution

Intel technology india pvt ltd – bangalore

Aug 2003 to May 2005

CAD Engineer

ü  Implemented an Extensible Framework to capture simulation results in to multiple Formats.

ü  Co-Owned Simulation based Logic Verification Engine to verify Register Transfer Level (RTL) Design specifications.


o    Enabled Logic Verification of Yonah and Merom (65nm technology) family of Intel Cores



ü  MS (Computer Engineering), University of Cincinnati, USA (Aug 2003)

ü  B.Tech (Computer Sc. & Engg.), Pondicherry University, India (May 2000)